Charge pumping system operation in the buck mode of the MCP1253DC-to-DC converter

Introduction

Integrated regulated charge-pump DC-to-DC converters are ever more widely used in various battery-powered mobile devices. Most manufacturers of electronic components offer integrated circuits (IC) intended for constructing boost converters, buck converters, or polar-inverting converters. However, just a small number of ICs can be used for obtaining regulated stabilised voltage both in the buck and in boost input voltage mode, e.g. ICs MAX1759 (Maxim Integrated Products), MCP1252/3 (Microchip Technology), and LTC3245 (Linear Technology) [1–3].

A range of possible input voltages given in the MCP1253 specifications [2] is 2.0…5.5 V. The output voltage provided by the converter lies within the range of 1.5…5.5 V. This is relevant on account of the starting transition of the present-day electronics to low voltage of 1.5 V. However, the basic specifications given in the description of this IC together with its modification, MCP1252, are incomplete and fail to cover all the modes of its application. For example, the dependence of output voltage on input voltage is only given for the output voltage nominal value equal to 3 V. Moreover, this dependence is given for integrated circuit MCP1252 only, having internal oscillator frequency of 650 kHz. For integrated circuit MCP1253 of the same family, with its oscillator frequency of 1 MHz, no data are available. Besides, there are no data for the dependence of output voltage on load current in different modes. The same is true for other characteristics as well.

A special mention shall be made of the IC operation algorithm. A description of MCP1252/3 given in the data sheet [2] fails to provide the necessary data about the algorithms of IC operation in different modes. The data sheet [2] describes one of the possible operation algorithms but does not specify the mode it relates to, and the switches used in the algorithm explanation are not shown in the functional block diagram. The application note [4] discusses just one algorithm of the IC operation, namely, the buck mode, but its implementation is not supported by the measurement results, and after the description of operation algorithms in other modes, a reference to the data sheet [2] is made, where these issues are not considered. The application note [4] provides a schematic of the charge pump system operation (Fig. 1).

Fig. 1. Charge pump system schematic [4]

According to the descriptions given in [2, 4], in the buck mode, switch SW1 is always closed, while switch SW2 is always open, and operation of the IC acting as converter and stabiliser in the steady-state condition consists of three phases. The first phase is that of transferring charge to flying capacitor CFLY, when switch SW3 is closed. It lasts for half of the internal oscillator period (Т / 2), with (Т / 2) = 500 ns. During the first phase the flying capacitor is connected to input V_IN, due to which it is charged. Upon completion of the first phase all switches are opened and the second phase (idle phase) starts. Hysteresis comparator U₂ compares the feedback voltage with the reference voltage, or, more exactly, with the voltage which is less than the reference voltage by the hysteresis voltage value. If the feedback voltage is below the regulation point, the device transitions to the third phase, i.e. that where the flying capacitor charge is transferred to the output capacitor C_OUT and load R_L. The third phase is implemented by opening of switch SW3 and closing of switch SW4, and can be of different duration, up to the half of the oscillator period. In this phase the feedback voltage is compared with the reference voltage again, but this time, more exactly, with voltage equal to the reference value, plus the hysteresis voltage value. If before expiry of a period of time corresponding to half of the oscillator period, the feedback voltage becomes equal to that voltage and the regulating system transitions back to the second stage. If the charge transfer occurring during half of the oscillator period is not enough for reaching the upper regulation threshold, after comparison the IC transitions to the first stage, i.e. the phase of flying capacitor charge during half of the period.

However, from the information given in [2, 4] it is not possible to infer how the charge pumping system will operate in the buck mode under different load currents, as well as at close values of the input and output voltages and in cases when the input voltages are much greater than the output ones. This actually was the purpose of this paper, which is a follow-up on a series of research whose first results were presented in the paper [5]. It should be mentioned that working on it required an expansion of the research methodology used in the paper [5] and described previously in [6–8].

Measurement methodology and object of research

In addition to earlier oscilloscope measurements of the variable component of regulated output voltage U_out~ and flying capacitor voltage U_fly+ (voltage between its positive pole and the ground), in this paper voltage across the negative pole of the flying capacitor U_fly – was measured. These measurements were taken when connected to the closed (U_fly~) and open (U_flyDC+ and U_flyDC–) oscilloscope inputs, which enabled to substantially simplify analysis of the obtained results and expand the potential for studying operation algorithms of the ICs of charge pump DC-to-DC converters.

Due to the fact that the results of preliminary measurements revealed a great influence of the magnitudes and ratios of U_in and U_out, as well as the magnitudes of I_out, on the charge pumping system operation, results for several typical modes were obtained. Notably, when using an input module of the measuring stand, as schematically shown in the paper [6], built on the base of applying an LM317 integrated circuit, which is a linear voltage stabiliser, there is a possibility to obtain only 8 discrete voltage values within the range of 1.6…5.3 V. These values were used as input voltages of the studied DC-to-DC converter. The output voltages of the DC-to-DC converter were regulated by means of a digital potentiometer in the feedback circuit of the studied integrated circuit MCP1253. Using it, one can obtain 256 discrete values of the output voltage within the range of 1.6…5.3 V with a small increment. The load used in this paper was represented by a resistor box enabling-load current regulation in any mode with a small increment. The most restrictions in selecting a research mode were associated with a small number of possible values of the input voltage U_in. Considering this, the input voltage values selected in this paper were those closest to the maximum, medium, and minimum voltage values of the 2.0…5.5 V range given in the data sheet [2]. The same goes for the output voltage U_out, for which the range of 1.5…5.5 V is set [2]. Here, additional consideration was given to the need to study converter operation both with large and small difference between input and output voltages. As regards the magnitudes of load currents, for each mode up to ten load current values were set from the operating range of 10…100 mА.

It is quite probable that over the period of MCP1253 integrated circuit manufacture the pumping system operation algorithm could be changing. Considering this, it should be mentioned that the results given below were obtained for an IC with marking 1253dj/012109.

Experiment results

Mode U_in = 5.1 V, U_out = 3.5 V. The main specific feature of this mode is great difference between the input and output voltage magnitudes. Fig. 2 shows some measurement results for comparatively low load currents. In the left-hand field, zero levels of signals are shown. Hereinafter, the odd digits correspond to flying capacitor voltages, and the even ones, to the output voltage. With load current increase, ripple frequency of output voltage U_out~ increases. In so doing, an increase of U_flyDC – starts simultaneously with that of U_out ~, and between their peaks, voltage U_flyDC– is close to zero.

Fig. 2. Signal waveforms (10 µs/div) of voltages U_flyDC– (100 mV/div) and U_out~ (20 mV/div) at U_in = 5.1 V, U_out = 3.5 V and under different load currents:
1, 2 – 11 mА; 3, 4 – 19 mА; 5, 6 – 30 mА

Fig. 3 shows variation of U_flyDC+ for the modes close to those given in Fig. 2. In all three cases, voltage U_flyDC+ for the most time is about 3.5 V, which is close to the output voltage U_out. At the moments corresponding to sharp rise of U_out~, peaks of U_flyDC+ appear. It means that during flying capacitor charging, simultaneously connected to input voltage V_IN are both CFLY and C_OUT (see Fig. 1). Such connection can be implemented by closing switches SW1, SW3, and SW4.

Fig. 3. Signal waveforms (5 µs/div) of voltages U_flyDC+ (1 V/div) and U_out~ (20 mV/div) at U_in = 5.1 V, U_out = 3.5 V and under different load currents:
1, 2 – 11 mА; 3, 4 – 19 mА; 5, 6 – 33 mА

Upon expiry of the time corresponding to half-period of the oscillator clock pulses, the idle state sets in, when only switch SW1 remains closed. Comparator U₂ compares feedback voltage with the sum value of reference voltage VREF and hysteresis voltage. If the feedback voltage has reached the upper limit of regulating system actuation, then the switches remain in the same position, and the regulation system starts comparing the feedback voltage with a magnitude equal to the difference of VREF and hysteresis voltage. If after the first charge transfer the feedback voltage has not reached the upper limit of regulating system actuation, then the first charge transfer is to be followed by a second one.

Fig. 4 provides details of the stage of single charge and flying capacitor disconnection, shown to a scale of 1 µs/div. In case of flying capacitor charging time taking 0.5 µs, the output voltage increases simultaneously, and after flying capacitor disconnection from the input voltage, voltage U_out starts decreasing slowly. An increase of voltage U_flyDC– in the course of charging does not depend of the load current and is approximately equal to 460 mV.

Fig. 4. Signal waveforms (1 µs/div) of voltages U_flyDC– (100 mV/div) and U_out~ (20 mV/div) at U_in = 5.1 V, U_out = 3.5 V under load currents of 11 mА, 19 mА, and 30 mA at the stage of charging and flying capacitor disconnection

The measurement results under higher load currents are given in Fig. 5. Same as under low load currents, an increase of the output voltage starts together with the start of flying capacitor charging. As the load current increases, transition
from single charge-pumping pulses occurs, first to alternation of single and paired pulses and then to paired pulses. An increase of voltage U_flyDC+ over the time of a single pulse amounted to approximately 480 mV, with each pumping pulse duration and the time interval between paired pulses being equal to 0.5 µs. An increase of voltage U_out~ under single pumping pulses amounted to approximately 30 mV, and under paired pulses – 60 mV. It follows that under high load currents, one charge transfer within a half-period of the oscillator cycle is not enough for reaching the upper limit of system actuation. Here a second charge transfer takes place, lasting a half-period as well, and this is what actually leads to an increase of the upper period of the output voltage regulating system actuation.

Fig. 5. Signal waveforms (2 µs/div) of voltages U_flyDC+ (1 V/div) and U_out~ (20 mV/div) at U_in = 5.1 V, U_out = 3.5 V and under different load currents:
1, 2 – 83 mA; 3, 4 – 19 mА; 5, 6 – 110 mА

Mode U_in = 5.1 V, U_out = 4.8 V. In this mode the difference between the input and output voltages is not great. The measurement results (Fig. 6), as was to be expected, differ from the previous mode. Paired charge transfer pulses for this mode were observed under all load currents below 46 mA, with the output voltage increasing by 36 mV. Under the current of 63 mA, transition from paired charge transfer pulses to triple ones would occur, with the output voltage increasing by 44 mV over three successive charge transfers. In so doing, in each pulse the flying capacitor voltage increases from the base level, which corresponds to the output voltage value, by approximately 160…170 mV, which is just slightly less than the difference between U_in and U_out. According to the obtained results, it can be concluded that under load currents of 46 and 63 mA, during charge transfer in this mode, same as in the previous one (U_in = 5.1 V, U_out = 3.5 V), capacitors CFLY and C_OUT are linked in parallel and connected to Cin and V_IN. However, under the current of 100 mA, with three consecutive charge transfers, the regulating system operated in a different mode (see Fig. 6).

It will be observed that in this case, after each charge transfer during 500 ns, flying capacitor would disconnect from the output voltage, which is demonstrated by large sags in U_flyDC+. Such mode would set in already under the current of 77 mA. In Fig. 7, the waveforms of signals for such mode are shown on a larger time scale (1 µs/div). However, unlike Fig. 6, voltage U_flyDC– is shown here, rather than U_flyDC+. It can be seen that in the sags of Uf_lyDC– the magnitude of this voltage is close to zero, which is another proof that the flying capacitor would disconnect from the output voltage during charging.

Fig. 6. Signal waveforms (2 µs/div) of voltages U_flyDC+ (1 V/div) and U_out~ (20 mV/div) at U_in = 5.1 V, U_out = 4.8 V and under different load currents:
1, 2 – 46 mА; 3, 4 – 63 mА; 5, 6 – 100 mА

It follows from the obtained results, as shown in Fig. 7, that after the first and the second discharges the flying capacitor is connected to U_in in parallel (switch SW2 is closed and the rest are open). When charge is transferred to load, the flying capacitor in this case is connected in series with U_in (switches SW2 and SW4 are closed and the rest are open). This is called a voltage doubler mode. Yet, if the difference between converter input and output voltages is small, even such mode cannot ensure transfer of the necessary charge under a high load current within a short period of time equal to half of the oscillator clock frequency (500 ns).

For that, three consecutive charge transfers are required, designated in Fig. 7 as stages 1, 3, and 5. Stages 1, 3, and 5 are the stages of charge transfer under operation in the voltage doubler mode, when the input voltage is connected in series with the flying capacitor voltage (switches SW2 and SW4 are closed, switches SW1 and SW3 are open). Stages 2 and 4 are the stages of flying capacitor charging. Each one of the stages 1–4 matches in time the duration of the oscillator half-period (500 ns).

Fig. 7. Signal waveforms (1 µs/div) of voltages: 1 – U_flyDC– (1 V/div); 2 – U_out~ (20 mV/div) at U_in = 5.1 V, U_out = 4.8 V and under load current of 77 mA

The hysteresis comparator keeps comparing reference voltage with the upper limit of regulating system operation in the voltage doubler mode. For this reason stage 5, in which charge transfer was performed, turned out to be shorter than stages 1 and 3. For three consecutive charge transfers, the upper limit of regulating system actuation turned out to be higher than normal, which resulted in the growth of the output voltage ripple span up to 70 mV. Such signal waveforms take place under load currents from 77 mA up to the limit values of 100 mА.

Mode U_in = 3.26 V, U_out = 3.02 V. Same as the previous mode, this one relates to the modes with small difference between the input and output voltages, but, unlike the previous one, the absolute values of those voltages are lower in this mode. Fig. 8 shows voltage waveforms under a small current equal to just 9 mA. Three different stages of regulating system operation can be seen. After the start of oscilloscope measurements on the downslope of U_flyDC– this voltage drops down to zero, which indicates disconnection of CFLY from the regulating system (all the keys are open). The flying capacitor remains in this state until U_out~, while decreasing, reaches the lower limit of hysteresis comparator actuation. When this occurs, the flying capacitor transitions to the first charge transfer stage, successively connecting to the input voltage for operation in the voltage doubler mode even under such low currents. It should be pointed out that with such connection, the noticeable spike of U_out~ shown in Fig. 8 is associated with operation of the switches and is not typical. An increase of voltage U_out~ with such connection amounts to 45 mV, which is the maximum value in the regulating system operation. Measurements taken with a smaller time scale division value have shown that the charge transfer time is equal to 500 ns (oscillator half-period).

Fig. 8. Signal waveforms (20 µs/div) of voltages: 1 – U_flyDC– (1 V/div); 2 – U_out~ (20 mV/div) at U_in = 3.26 V, U_out = 3.02 V and under load current of 9 mA

The first charge transfer stage is followed by two others, with smaller values of voltage U_out~ increase. Upon transfer completion and CFLY disconnection from load, voltage U_flyDC– on the flying capacitor slowly decreases and at the moment of regulating system actuation as per the lower limit of hysteresis comparator amounts to approximately 1.6 V. It occurs after 38 ms from the starting moment of C_OUT first discharge stage. At that moment the flying capacitor still has a considerable charge, with voltage on it amounting to about 1.6 V when connected to the input voltage, and increasing to approximately 2.8 V during the second charge transfer. During the second charge transfer, output capacitor C_OUT is connected to CFLY, connected in series to the input voltage V_IN. In this case the output voltage U_out~ increases by 35 mV, i.e. by a value which is less than in the first charge. The second stage of U_flyDC– decrease lasts approximately 14 µs, and the third stage of U_out~ decrease, which follows, is shorter still, lasting about 10 µs. Upon completion of the third charge transfer, the flying capacitor disconnects from the circuit (idle state, all switches open).

With an increase of load current, the character of regulating system operation changes. Fig. 9 shows voltage waveforms under the load current of 45 mA. It can be seen that the threestage pattern of system operation, shown in Fig. 8, is replaced by a two-stage one, in which a 40 mV increase of U_out~ alternates with an increase by approximately 34 mV, and on U_flyDC– a slightly inclined upper plateau appears at a voltage of approximately 2.3 V. Due to a smaller time scale division value, the details of peaks on U_flyDC–, associated with charge transfer, are well visible in Fig. 9. In particular, it can be seen that upon flying capacitor disconnection for transition to the idle state, there is a ledge on the U_flyDC– downslope curve, which reproduces well.

Fig. 9. Signal waveforms (2 µs/div) of voltages: 1 – U_flyDC– (1 V/div); 2 – U_out~ (20 mV/div) at U_in = 3.26 V, U_out = 3.02 V and under load current of 45 mA

With further load current increase, the slightly inclined upper plateau on U_flyDC– gradually shrinks and under the current of 88 mA vanishes completely (Fig. 10). In each cycle, the rise of U_out~, amounting to 40 mV, takes place during CFLY charging, which lasts 500 ns, i.e. half of the oscillator period. Once this time has expired, voltage at the output and on the flying capacitor starts decreasing due to transition to the normal idle state, when all the switches are open.

Fig. 10. Signal waveforms (2 µs/div) of voltages: 1 – U_flyDC– (1 V/div); 2 – U_out~ (20 mV/div) at U_in = 3.26 V, U_out = 3.02 V and under load current of 88 mA

Mode U_in = 2.52 V, U_out = 1.71 V. Shown in Fig. 11 are three sets of U_flyDC– and U_out~ waveforms under three load current values covering the
entire range of its conversion. Under load current variations, the character of U_flyDC– and U_out~ remains the same, with only the frequency of cycles “charge transfer – flying capacitor disconnection” changing. The start of a rise coincides in time with the start of flying capacitor charging, and the end of U_out~ rise – with its disconnection. In this mode, the character of U_flyDC– and U_out~ change is similar to that observed for the mode of U_in = 5.1 V, Uout = = 3.5 V, in which the input voltage considerably exceeded the output.

Fig. 11. Signal waveforms (5 µs/div) of voltages U_flyDC– (200 V/div) and U_out~ (20 mV/div) at U_in = 2.52 V, U_out = 1.71 V and under different load currents:
1, 2 – 19 mA; 3, 4 – 46 mА; 5, 6 – 92 mА

Mode U_in = 2.59 V, U_out = 2.18 V. Fig. 12 shows some results for almost the same input voltage value as in the previous mode, but with the output voltage closer to the input value. With an increase of load current for rising the output voltage from the lower to the upper limit of regulating system actuation, transition from single pulse to three consecutive charge pumping pulses occurs. In so doing, the ripple period of U_out~ remains constant, equal to approximately 4.3 µs, and the difference between the upper and the lower levels ∆U_out~ of those ripples is changing non-monotonously. If under the load current of 36 mA a single charge transfer with the duration of 500 ns is sufficient, and ∆U_{out ~} = 20 mV, then with the load current of 68 mA it is already two charge transfers that are required, and ∆U_out~ = 30 mV. Under the load current of 101 mA, ∆U_out~ = 22 mV is reached over three consecutive charge transfers.

Fig. 12. Signal waveforms (2 µs/div) of voltages U_flyDC– (500 V/div) and U_out~ (10 mV/div) at U_in = 2.59 V, U_out = 2.18 V and under different load currents:
1, 2 – 101 mА; 3, 4 – 68 mА; 5, 6 – 36 mА

It follows from these measurements that lying at the base of regulating system operation in this mode are not the hysteresis comparator actuation thresholds, but rather the time. The regulating system does not transition to the voltage doubler mode even under the limit load currents.

Mode U_in = 2.17 V, U_out = 1.71 V. Shown in Fig. 13 as an example are the waveforms for four pairs of voltages U_flyDC– and U_out~ under different load currents. It can be seen that for this mode, with an increase of the load current, the output voltage regulating system increases the number of U_flyDC– consecutive pulses. Notably, in each of the sequences the amplitude of the first pulse is, as a rule, smaller than that of the rest. The amplitude of U_out~ ripples is about 20 mV, however it is somewhat different for different load currents, and sometimes even for the same load current. The regulating system, same as in the previous mode, does not transition to operation in the voltage doubler state under high load currents.

Fig. 13. Signal waveforms (2 µs/div) of voltages U_flyDC– (200 V/div) and U_out~ (10 mV/div) at U_in = 2.17 V, U_out = 1.71 V and under different load currents:
1, 2 – 19 mA; 3, 4 – 45 mA; 5, 6 – 68 mA; 7, 8 – 99 mA

Conclusion

Based on the results of research conducted on the MCP1253 charge pump voltage converter operating in the buck mode, it has been established that the integrated circuit three-phase operation algorithm described in [2, 4] is not reflective of the real algorithm of its operation. Even when the input voltage is much higher than the output, charge transfer within the half-duration of clock pulses occurs, contrary to the described algorithm, with simultaneous connection of the flying and output capacitors to the input voltage. Under high load currents, a single transfer within one clock pulse cycle is not enough, so the regulating system transitions to paired charge transfer pulses.

At high values of the input and output voltages and small difference of their magnitudes, charge transfer also occurs under simultaneous connection of the flying and output capacitors to the input voltage and implementation of pumping by means of paired and triple pulses. However, under load currents over 60 mA, the regulating system operates in the voltage doubler mode; moreover, after two or three consecutive charge transfers the system will not transition to the idle state, when all the switches are open, and the flying capacitor will remain connected to the input voltage. Application of a two-stage or three-stage charge transfer leads in this case to an increase of the output voltage ripple amplitude.

With low values of the input and output voltages and small difference between them (V_IN = 3.26 V, VOUT = 3.02 V), the regulating system operates in the voltage doubler mode starting from low load currents. In this case, after a threestage charge transfer the system transitions to the idle state (all the switches are open). With an increase of the load current, the system transitions to the two-stage charge transfer mode, in which transition to the idle state alternates with a state when the flying capacitor remains connected to the input current. With further increase of the load current, the system provides regulation only when using charge transfer in the mode of voltage doubler and transition to the idle state. The necessary amount of transferred charge in this case is achieved due to essential increase of the transfer cycles frequency.

Under small values of the input voltage (V_IN ~ 2.5 V) and high relative differences between the input and output voltages, the regulating system operates in a mode when during charge transfer the flying capacitor is connected to the input voltage, same as in all cases when the voltage doubler mode is not used. The necessary amount of charge transferred under different load currents within a single cycle is provided both due to an increase of transfer cycles per unit of time and at the expense of reducing the time of system residing in the idle state in between the cycles.

The research findings presented in the paper were obtained within the framework of the government task order No. 8.5577.2017/8.9 for carrying out a project on the subject “Investigation into noise characteristics and ripples of microcircuits of mobile secondary power supplies”, set by the Ministry of Education and Science of the Russian Federation.